1. Field of the Invention
The present invention relates to a clock generation circuit and the method thereof, especially to a clock generation circuit and the method thereof that utilize a reference clock inside a chip to generate an accurate clock.
2. Description of Related Art
Please refer to FIG. 1, illustrating a functional block diagram of a conventional image processing module. The image processing module comprises a circuit board 100. An image processing chip 110, which is mounted on the circuit board 100, comprises a clock adjusting circuit 112 and a micro controller 114. In addition to the image processing chip 110, the circuit board 100 further comprises a crystal oscillator 120, a HDMI (High-Definition Multimedia Interface)/MHL (Mobile High-Definition Link) port 130, a DVI (Digital Visual Interface)/DP (DisplayPort) port 140, a VGA (Video Graphics Array) port 150, an EEPROM (electrically erasable programmable read only memory) 160, a USB (universal serial bus) control chip 170, an LVDS (Low-voltage differential signaling) port 180, and an LED (light emitting diode) module port 190. The image processing chip 110 receives image data in digital or analog format through the HDMI/MHL port 130, the DVI/DP port 140, or the VGA port 150, performs format conversion or scaling on the image data, and then outputs the processed image data to a display panel through the LVDS port 180 and controls an LED backlight of the display panel through the LED module port 190. The image processing chip 110 also accesses the EEPROM 160 and communicates with external USB devices, such as flash memories, through the USB control chip 170.
In the above processes, the micro controller 114 of the image processing chip 110 has to refer to a stable working clock to perform the tasks. For example, after the image processing chip 110 receives image signal through the HDMI/MHL port 130, the DVI/DP port 140 or the VGA port 150, preliminary data will be obtained through processes in the front-end, such as data sampling and decoding, and then image data that are ready for display will be obtained by performing subsequent processes, such as image interpolation, color correction, contrast enhancement, on the preliminary data. Further, the image processing chip 110 stabilizes the image data by using a FIFO (first in first out) buffer when the image data is being outputted. Besides, if the image signal is an analog signal in VGA format, the micro controller 114 must further sample an Hsync (horizontal synchronization) signal and/or a Vsync (vertical synchronization) signal of the image signal to determine a mode of the image signal. Therefore, a reference clock is required for the image processing chip 110 to complete the above tasks. Conventionally, a crystal oscillator 120, which is not affected by a manufacturing process of the chip and an operating temperature, is installed on the circuit board 100 to provide a rather accurate reference clock. As shown in FIG. 1, the reference clock generated by the crystal oscillator 120 is inputted to the image processing chip 110; then the frequency and the phase of the reference clock are adjusted by the clock adjusting circuit 112 to form a working clock with a frequency required by the micro controller 114. In general, the clock adjusting circuit 112 can be implemented by an integer-N PLL (phase-locked loop) or a fractional-N PLL, depending on a ratio between the frequencies of the working clock and the reference clock.
However, the crystal oscillator 120 not only increases the area of the circuit board 100, but increases the winding length. The longer the winding length is, the easier the circuit board 100 and the components thereon are affected by electromagnetic interference. In addition, the crystal oscillator 120 also increase the overall cost of an image processing module. If the crystal oscillator 120 can be saved in each module, a great deal of cost can be saved when then quantity is huge. As a result, approaches of replacing the crystal oscillator outside the chip with a built-in reference clock generation circuit inside the chip are proposed. Please refer to FIG. 2, illustrating a functional block diagram of implementing a reference clock generation circuit inside a chip. The chip 200 in FIG. 2 comprises a reference clock generation circuit 210, a clock adjusting circuit 220, and a micro controller 230. Similar to the image processing chip 110, inside the chip 200 the phase and the frequency of the reference clock are adjusted by the clock adjusting circuit 220 to generate the working clock required by the micro controller 230; however, the chip 200 has the reference clock generation circuit 210 to provide the reference clock. In practical, the reference clock generation circuit 210 can be implemented by the LC tanks shown in FIGS. 3 and 4. The LC tanks in FIGS. 3 and 4 comprise inductors 310 and 320, capacitors 330 and 340, and transistors 350 and 360, and the LC tank in FIG. 4 further comprises a transistor 370. The principles of the LC tank are well known to people having ordinary skill in the art. Unfortunately, the LC tanks are subject to frequency drift due to temperature variations. The LC tank experiences a rising temperature in its environment as the working time of the chip 200 increases, which causes the frequency of the reference clock to decrease. As a result, the frequency of the working clock decreases as well, which causes the system to encounter errors. For example, if the chip 200 is an image processing chip, the error may cause mistakes in output images or even result in blank images.